1. Field of Invention
This invention relates generally to PMOS semiconductor memories and specifically to switching a word line of a PMOS non-volatile memory array between multiple potential levels.
2. Description of Related Art
Non-volatile memories such as, for instance, EEPROM and Flash EEPROM, include a plurality of memory cells contained within an array. Typically, the memory cells are floating gate MOS transistors having a source, a drain, a floating gate, and a control gate. Since such floating gate memory cells are programmed by inducing the accumulation of electrons on the floating gate and erased by discharging electrons from the floating gate, the threshold voltage (V.sub.T) of a programmed cell is more positive than that of an erased cell. It is the difference between the program V.sub.T and the erase V.sub.T of a cell which determines the "binary state"of the cell. For instance, a programmed cell represents the binary value "1", and an erased cell represents the binary value binary "0". To read the binary state of a cell, a read voltage which lies between the program V.sub.T and the erase V.sub.T is applied to the control gate of the cell. Thus, if the cell is an NMOS device, the cell conducts a channel current if in an erased state and, conversely, if the cell is a PMOS device, the cell conducts a channel current if in a programmed state.
FIG. 1 shows a PMOS floating gate memory cell 10 in accordance with that disclosed in U.S. Pat. No. 5,687,118, issued to Chang on Nov. 11, 1997. Cell 10 includes a channel region 20 extending between p+ source 16 and p+ drain 18 regions formed in an n- well 12 of a p- substrate 14. A floating gate 22 is insulated from the surface of n- well 12 by a thin tunnel oxide layer 24. A control gate 26 overlies floating gate 22. During programming and erasing operations of an array of cells 10, such as that disclosed in the co-pending U.S. patent application Ser. No. 08/911,968 entitled "Non-volatile Memory Array Architecture" and Ser. No. 08/947,850 entitled "Non-volatile PMOS Two-Transistor Memory Cell and Array", it is necessary to switch the word lines of the array (not shown) of cells 10 between multiple potential levels.
For instance, during programming operations, selected word lines are typically driven to a high positive potential such as, for instance, 9 volts, while un-selected word lines are held at lower voltages such as, for instance, 3 volts. During erasing operations, selected word lines are driven to a negative voltage such as -9 volts, while un-selected word lines are held at a floating potential. Thus, thus is a need for a circuit that is capable of switching the word lines of an associated memory array between a high positive potential, a high negative potential, an intermediate potential, and a floating potential.